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"Packet Processing Architecture Using Last-Level-Cache Slices and ..."
Tomohiro Korikawa et al. (2020)
- Tomohiro Korikawa
, Akio Kawabata
, Fujun He
, Eiji Oki
:
Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM. IEEE Access 8: 59290-59304 (2020)
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