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"Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET ..."
Chung-Kuan Cheng et al. (2022)
- Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin:
Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform. IEEE Access 10: 65971-65981 (2022)
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