"FPGA IP Core for DC Motor Control With Adaptive Neural Network PID Tuning, ..."

Naveen C et al. (2024)

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DOI: 10.1109/ACCESS.2024.3491995

access: open

type: Journal Article

metadata version: 2024-11-30

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Naveen C, Sandeep Singh Chauhan, C. Paramasivam, Veerpratap P. Meena:
FPGA IP Core for DC Motor Control With Adaptive Neural Network PID Tuning, and High-Resolution Encoder Interface. IEEE Access 12: 169356-169369 (2024)

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