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"Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative ..."

Grace Li Zhang et al. (2018)

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DOI: 10.1109/TCAD.2017.2702632

access: closed

type: Journal Article

metadata version: 2023-11-12

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Grace Li Zhang, Bing Li, Jinglan Liu, Yiyu Shi, Ulf Schlichtmann:
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 392-405 (2018)

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