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"An Efficient Timing Model for CMOS Combinational Logic Gates."

Chung-Yu Wu et al. (1985)

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DOI: 10.1109/TCAD.1985.1270164

access: closed

type: Journal Article

metadata version: 2020-09-24

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  - https://dblp.org/rec/journals/tcad/WuHCC85
Chung-Yu Wu, Jen-Sheng Hwang, Chin Chang, Ching-Chu Chang:
An Efficient Timing Model for CMOS Combinational Logic Gates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(4): 636-650 (1985)

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