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"VERILAT: verification using logic augmentation and transformations."
Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan (2000)
- Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan:
VERILAT: verification using logic augmentation and transformations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 1041-1051 (2000)
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