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"Built-In Test Sequence Generation for Synchronous Sequential Circuits ..."

Irith Pomeranz, Sudhakar M. Reddy (2002)

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DOI: 10.1109/12.995451

access: closed

type: Journal Article

metadata version: 2017-05-20

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  persistent URL:
  - https://dblp.org/rec/journals/tc/PomeranzR02
Irith Pomeranz, Sudhakar M. Reddy:
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times. IEEE Trans. Computers 51(4): 409-419 (2002)

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