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ORCID"High-Speed Area-Efficient Multiplier Design Using Multiple-Valued ..."
Shoji Kawahito et al. (1994)
- Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi:
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. IEEE Trans. Computers 43(1): 34-42 (1994)
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