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"A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache."

Stefan Rusu et al. (2007)

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DOI: 10.1109/JSSC.2006.885041

access: closed

type: Journal Article

metadata version: 2020-08-30

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  - https://dblp.org/rec/journals/jssc/RusuTMACCSBVLLV07
Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora:
A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. IEEE J. Solid State Circuits 42(1): 17-25 (2007)

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