"Design and FPGA implementation of an MPEG based video scalar with reduced ..."

Seetharaman Ramachandran, S. Srinivasan (2005)

> Home

Details and statistics

DOI: 10.1016/J.SYSARC.2004.07.008

access: closed

type: Journal Article

metadata version: 2021-01-15

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jsa/RamachandranS05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jsa/RamachandranS05
Seetharaman Ramachandran, S. Srinivasan:
Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization. J. Syst. Archit. 51(6-7): 435-450 (2005)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.