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"A Refinement Methodology for Clock Gating Optimization at Layout Level in ..."

Luca Benini et al. (2010)

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DOI: 10.1166/JOLPE.2010.1055

access: closed

type: Journal Article

metadata version: 2023-09-30

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Luca Benini, Alberto Bocca, Alberto Bonanno, Alberto Macii, Enrico Macii, Jean-Luc Nagel, Christian Piguet, Massimo Poncino:
A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits. J. Low Power Electron. 6(1): 44-55 (2010)

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