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ORCID"Design optimization for capacitive-resistively driven on-chip global ..."
Jianfei Jiang et al. (2015)
- Jianfei Jiang, Weifeng He, Jizeng Wei, Qin Wang, Zhigang Mao:
Design optimization for capacitive-resistively driven on-chip global interconnect. IEICE Electron. Express 12(8): 20150111 (2015)
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