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"Parallel Logic Simulation of VLSI Systems."

Mary L. Bailey, Jack V. Briner Jr., Roger D. Chamberlain (1994)

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DOI: 10.1145/185403.185424

access: closed

type: Journal Article

metadata version: 2018-11-06

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  - https://dblp.org/rec/journals/csur/BaileyBC94
Mary L. Bailey, Jack V. Briner Jr., Roger D. Chamberlain:
Parallel Logic Simulation of VLSI Systems. ACM Comput. Surv. 26(3): 255-294 (1994)

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