Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration ..."

Leandro D. Medus et al. (2019)

> Home

Details and statistics

DOI: 10.1109/ACCESS.2019.2920885

access: open

type: Journal Article

metadata version: 2021-07-25

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/access/MedusIFBM19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/access/MedusIFBM19
Leandro D. Medus, Taras Iakymchuk, José Vicente Francés-Víllora, Manuel Bataller-Mompeán, Alfredo Rosado Muñoz:
A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks. IEEE Access 7: 76084-76103 (2019)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.