"Using Arithmetic Transform for Verification of Datapath Circuits via Error ..."

Katarzyna Radecka, Zeljko Zilic (2000)

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DOI: 10.1109/VTEST.2000.843855

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Katarzyna Radecka, Zeljko Zilic:
Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. VTS 2000: 271-280

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