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"An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver ..."

Kevin Zheng et al. (2018)

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DOI: 10.1109/VLSIC.2018.8502377

access: closed

type: Conference or Workshop Paper

metadata version: 2018-10-30

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Kevin Zheng, Yohan Frans, Sai Lalith Ambatipudi, Santiago Asuncion, Hari Teja Reddy, Ken Chang, Boris Murmann:
An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS. VLSI Circuits 2018: 269-270

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