"A 4×4-bit multiplier LSI implementation of two phase clocking ..."

Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine (2015)

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DOI: 10.1109/NEWCAS.2015.7182098

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-02

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Kazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine:
A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic. NEWCAS 2015: 1-4

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