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"A Low Power, High Performance Threshold Logic-Based Standard Cell ..."

Samuel Leshner et al. (2010)

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DOI: 10.1109/ISVLSI.2010.32

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/isvlsi/LeshnerBYCPV10
Samuel Leshner, Krzysztof S. Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, Sarma B. K. Vrudhula:
A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS. ISVLSI 2010: 210-215

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