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"Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI ..."

Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas (2008)

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DOI: 10.1109/ISQED.2008.4479695

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - conf/isqed/RaghunandanSS08
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  persistent URL:
  - https://dblp.org/rec/conf/isqed/RaghunandanSS08
Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas:
Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects. ISQED 2008: 43-46

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