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"A practical clock tree synthesis for semi-synchronous circuits."

Masahiko Toyonaga et al. (2000)

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DOI: 10.1145/332357.332393

access: closed

type: Conference or Workshop Paper

metadata version: 2023-05-01

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  dblp key:
  - conf/ispd/ToyonagaKYT00
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  - https://dblp.org/rec/conf/ispd/ToyonagaKYT00
Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi:
A practical clock tree synthesis for semi-synchronous circuits. ISPD 2000: 159-164

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