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"A 12-Bit 3.3MS/S pipeline cyclic ADC with correlated level shifting technique."

Koken Chin et al. (2017)

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DOI: 10.1109/ISPACS.2017.8266549

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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  dblp key:
  - conf/ispacs/ChinMWTSMH17
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  - https://dblp.org/rec/conf/ispacs/ChinMWTSMH17
Koken Chin, Yuta Mishima, Yuki Watanabe, Hiroyuki Tsuchiya, Hao San, Tatsuji Matsuura, Masao Hotta:
A 12-Bit 3.3MS/S pipeline cyclic ADC with correlated level shifting technique. ISPACS 2017: 602-605

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