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"An FPGA-based implementation of the MINRES algorithm."

David Boland, George A. Constantinides (2008)

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DOI: 10.1109/FPL.2008.4629967

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-15

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  dblp key:
  - conf/fpl/BolandC08
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  - https://dblp.org/rec/conf/fpl/BolandC08
David Boland, George A. Constantinides:
An FPGA-based implementation of the MINRES algorithm. FPL 2008: 379-384

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