"Compiling VHDL into a high-level synthesis design representation."

Petru Eles et al. (1992)

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DOI: 10.1109/EURDAC.1992.246333

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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  - https://dblp.org/rec/conf/eurodac/ElesKPM92
Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Marius Minea:
Compiling VHDL into a high-level synthesis design representation. EURO-DAC 1992: 604-609

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