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"Power and Delay Reduction via Simultaneous Logic and Placement ..."

Balakrishna Kumthekar, Fabio Somenzi (2000)

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DOI: 10.1109/DATE.2000.840039

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Balakrishna Kumthekar, Fabio Somenzi:
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs. DATE 2000: 202-207

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