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"A Practical Gate Resizing Technique Considering Glitch Reduction for Low ..."

Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru (1999)

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DOI: 10.1145/309847.309977

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru:
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. DAC 1999: 446-451

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