"High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog."

Arash Saifhashemi, Peter A. Beerel (2005)

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DOI: —

access: closed

type: Conference or Workshop Paper

metadata version: 2012-03-23

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  dblp key:
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Arash Saifhashemi, Peter A. Beerel:
High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog. CPA 2005: 275-288

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