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"Easing the verification bottleneck using high level synthesis."

D. Varma, D. Mackay, P. Thiruchelvam (2010)

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DOI: 10.1109/VTS.2010.5469565

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-25

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  - conf/vts/VarmaMT10
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D. Varma, D. Mackay, P. Thiruchelvam:
Easing the verification bottleneck using high level synthesis. VTS 2010: 253-254

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