"A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide-Based Full ..."

Koichiro Zaitsu et al. (2022)

> Home

Details and statistics

DOI: 10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830372

access: closed

type: Conference or Workshop Paper

metadata version: 2023-05-31

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsit/ZaitsuMNTYSWANN22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsit/ZaitsuMNTYSWANN22
Koichiro Zaitsu, Akira Matsumoto, Mizuki Nishida, Yusuke Tanaka, Hirofumi Yamashita, Yosuke Satake, Takashi Watanabe, Kunihiko Araki, Naoki Nei, Keiichi Nakazawa, Junpei Yamamoto, Mutsuo Uehara, Hiroyuki Kawashima, Yusaku Kobayashi, Tomoyuki Hirano, Keiji Tatani:
A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide-Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency. VLSI Technology and Circuits 2022: 286-287

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.