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"A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller ..."

Xiaohui Lin, Mohamed Megahed, Tejasvi Anand (2022)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830355

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-10

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Xiaohui Lin, Mohamed Megahed, Tejasvi Anand:
A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail. VLSI Technology and Circuits 2022: 188-189

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