"A 0.9V Rail-to-Rail Ultra-Low-Power Fully Integrated Clock Generator ..."

Sander Derksen et al. (2024)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46783.2024.10631535

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type: Conference or Workshop Paper

metadata version: 2024-10-17

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Sander Derksen, Maël Demarets, Gerard Villar Pique, Fabio Sebastiano:
A 0.9V Rail-to-Rail Ultra-Low-Power Fully Integrated Clock Generator Achieving 23fJ/Cycle in 28nm CMOS. VLSI Technology and Circuits 2024: 1-2

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