"Scaling Dual-Gate Ultra-thin a-IGZO FET to 30 nm Channel Length with ..."

Kaifei Chen et al. (2022)

> Home

Details and statistics

DOI: 10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830389

access: closed

type: Conference or Workshop Paper

metadata version: 2025-02-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsit/ChenNYLLLHDLWWL22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsit/ChenNYLLLHDLWWL22
Kaifei Chen, Jiebin Niu, Guanhua Yang, Menggan Liu, Wendong Lu, Fuxi Liao, Kailiang Huang, XinLv Duan, Congyan Lu, Jiawei Wang, Lingfei Wang, Mengmeng Li, Di Geng, Chao Zhao, Guilei Wang, Nianduan Lu, Ling Li, Ming Liu:
Scaling Dual-Gate Ultra-thin a-IGZO FET to 30 nm Channel Length with Record-high Gm, max of 559 µS/µm at VDS=1 V, Record-low DIBL of 10 mV/V and Nearly Ideal SS of 63 mV/dec. VLSI Technology and Circuits 2022: 298-299

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.