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"A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder ..."

Anuj Verma, Rahul Shrestha (2020)

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DOI: 10.1109/VLSID49098.2020.00018

access: closed

type: Conference or Workshop Paper

metadata version: 2022-11-14

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Anuj Verma, Rahul Shrestha:
A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio. VLSID 2020: 1-6

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