"Tutorial T5: High Performance Low Power Designs - Challenges and Best ..."

Nagesh Tamarapalli, Prashanth Vallur, Sachin Kulkarni (2015)

> Home

Details and statistics

DOI: 10.1109/VLSID.2015.113

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/TamarapalliVK15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/TamarapalliVK15
Nagesh Tamarapalli, Prashanth Vallur, Sachin Kulkarni:
Tutorial T5: High Performance Low Power Designs - Challenges and Best practices in Design, Verification and Test. VLSID 2015: 10-11

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.