"A Technique for Throughput and Register Optimization during Resource ..."

Nagendran Rangan, Karam S. Chatha (2005)

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DOI: 10.1109/ICVD.2005.35

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Nagendran Rangan, Karam S. Chatha:
A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling. VLSI Design 2005: 564-569

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