"Circuit optimization for minimisation of power consumption under delay ..."

S. C. Prasad, Kaushik Roy (1995)

> Home

Details and statistics

DOI: 10.1109/ICVD.1995.512129

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/PrasadR95
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/PrasadR95
S. C. Prasad, Kaushik Roy:
Circuit optimization for minimisation of power consumption under delay constraint. VLSI Design 1995: 305-309

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.