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ORCID"Post Assembly Timing Closure for Multi Million Gate Chips."
Shashank Prasad et al. (2010)
- Shashank Prasad, Dongzi Liu, Oleg Levitsky, Dave Noice, Shailendra Srivastava:
Post Assembly Timing Closure for Multi Million Gate Chips. VLSI Design 2010: 75-80
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