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"Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis."

Vinay C. Patil et al. (2013)

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DOI: 10.1109/VLSID.2013.167

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/PatilSBK13
Vinay C. Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu:
Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis. VLSI Design 2013: 80-85

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