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"Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin ..."

Jyoti Patel et al. (2022)

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DOI: 10.1109/VLSID2022.2022.00063

access: closed

type: Conference or Workshop Paper

metadata version: 2022-09-29

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Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta:
Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications. VLSID 2022: 292-296

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