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"FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with ..."

Ayan Palchaudhuri, Anindya Sundar Dhar (2024)

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DOI: 10.1109/VLSID60093.2024.00109

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-08

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Ayan Palchaudhuri, Anindya Sundar Dhar:
FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation. VLSID 2024: 617-622

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