"Modeling and Reduction of Gate Leakage during Behavioral Synthesis of ..."

Saraju P. Mohanty, Elias Kougianos (2006)

> Home

Details and statistics

DOI: 10.1109/VLSID.2006.118

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/MohantyK06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/MohantyK06
Saraju P. Mohanty, Elias Kougianos:
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits. VLSI Design 2006: 83-88

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.