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"A Fast Equation Free Iterative Approach to Analog Circuit Sizing."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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Supriyo Maji, Pradip Mandal (2012)

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DOI: 10.1109/VLSID.2012.99

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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Supriyo Maji, Pradip Mandal:
A Fast Equation Free Iterative Approach to Analog Circuit Sizing. VLSI Design 2012: 370-375

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last updated on 2023-09-30 09:58 CEST by the dblp team

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