"Using a Balanced Quad List Quad Tree to Speed Up a Hierarchical VLSI ..."

Pei-Yung Hsiao, Lih-Der Jang (1992)

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DOI: 10.1109/ICVD.1992.658091

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Pei-Yung Hsiao, Lih-Der Jang:
Using a Balanced Quad List Quad Tree to Speed Up a Hierarchical VLSI Compaction Scheme. VLSI Design 1992: 370-371

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