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"High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction ..."

Kunal Desai et al. (2010)

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DOI: 10.1109/VLSI.DESIGN.2010.104

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Kunal Desai, Rajasekhar Nagulapalli, Vijay Krishna, Rajkumar Palwai, Pravin Kumar Venkatesan, Vijay Khawshe:
High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique. VLSI Design 2010: 300-305

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