BibTeX record conf/vlsid/AsthanaLM94

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@inproceedings{DBLP:conf/vlsid/AsthanaLM94,
  author    = {Abhaya Asthana and
               Mike Laznovsky and
               Boyd Mathews},
  title     = {{SEMU:} {A} Parallel Processing System for Timing Simulation of Digital
               {CMOS} {VLSI} Circuits},
  booktitle = {Proceedings of the Seventh International Conference on {VLSI} Design,
               {VLSI} Design 1994, Calcutta, India, January 5-8, 1994},
  pages     = {33--38},
  publisher = {{IEEE} Computer Society},
  year      = {1994},
  url       = {https://doi.org/10.1109/ICVD.1994.282634},
  doi       = {10.1109/ICVD.1994.282634},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/conf/vlsid/AsthanaLM94.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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