"A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS."

Bob Verbruggen et al. (2014)

Details and statistics

DOI: 10.1109/VLSIC.2014.6858451

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-02

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