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"A shorted global clock design for multi-GHz 3D stacked chips."

Liang-Teck Pang et al. (2012)

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DOI: 10.1109/VLSIC.2012.6243844

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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  dblp key:
  - conf/vlsic/PangRWSFM12
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  - https://dblp.org/rec/conf/vlsic/PangRWSFM12
Liang-Teck Pang, Phillip J. Restle, Matthew R. Wordeman, Joel A. Silberman, Robert L. Franch, Gary W. Maier:
A shorted global clock design for multi-GHz 3D stacked chips. VLSIC 2012: 170-171

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