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"A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core ..."

Shunsuke Okumura et al. (2019)

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DOI: 10.23919/VLSIC.2019.8778187

access: closed

type: Conference or Workshop Paper

metadata version: 2019-08-05

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Shunsuke Okumura, Makoto Yabuuchi, Kenichiro Hijioka, Koichi Nose:
A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm². VLSI Circuits 2019: 248-

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