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"A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI ..."

Jinwook Oh et al. (2020)

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DOI: 10.1109/VLSICIRCUITS18222.2020.9162917

access: closed

type: Conference or Workshop Paper

metadata version: 2023-08-19

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  dblp key:
  - conf/vlsic/OhLKZSAVFGCWMBB20
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  persistent URL:
  - https://dblp.org/rec/conf/vlsic/OhLKZSAVFGCWMBB20
Jinwook Oh, Sae Kyu Lee, Mingu Kang, Matthew M. Ziegler, Joel Silberman, Ankur Agrawal, Swagath Venkataramani, Bruce M. Fleischer, Michael Guillorn, Jungwook Choi, Wei Wang, Silvia M. Mueller, Shimon Ben-Yehuda, James Bonanno, Nianzheng Cao, Robert Casatuta, Chia-Yu Chen, Matt Cohen, Ophir Erez, Thomas W. Fox, George Gristede, Howard Haynie, Vicktoria Ivanov, Siyu Koswatta, Shih-Hsien Lo, Martin Lutz, Gary W. Maier, Alex Mesh, Yevgeny Nustov, Scot Rider, Marcel Schaal, Michael Scheuermann, Xiao Sun, Naigang Wang, Fanchieh Yee, Ching Zhou, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang:
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. VLSI Circuits 2020: 1-2

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