"A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge ..."

Ying-Zu Lin et al. (2016)

> Home

Details and statistics

DOI: 10.1109/VLSIC.2016.7573536

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/LinTTL16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/LinTTL16
Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Chao-Hsin Lu:
A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS. VLSI Circuits 2016: 1-2

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.