"Power-aware SoC test optimization through dynamic voltage and frequency ..."

Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal (2013)

> Home

Details and statistics

DOI: 10.1109/VLSI-SOC.2013.6673258

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsi/SheshadriAA13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsi/SheshadriAA13
Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal:
Power-aware SoC test optimization through dynamic voltage and frequency scaling. VLSI-SoC 2013: 102-107

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.